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- Introduction to Digital Design, FPGA, and VHDL - VHDL Concurrent and Sequential Statements, Signals, Operators, Arrays, and Test Benches.- Structural Design using “Component” - Generate Statement - Generic Statement- Implementation of different projects [Decoder, MUX, 4-bit and 16-bit Full Adder, Synch. and Async. Set/reset Registers, ALU, 2-bit Adder test bench, Serial to Parallel Converter and Parallel to Serial Converter, Finite State Machine, and FIR Filter.- Implementation of ROM using Xilinx Core Generator- Practice Generating HDL Code from MATLAB Simulink Steps and Tips and Tricks.
The first day includes:1. Introduction to E-waste2. Definition and components of e-waste3. Problem and solutions to e-waste generation4. E-waste in Egypt5. E-waste management in Egypt6. Vision for Egypt7. Health impacts of e-waste8. Overview of environmental impacts9. Worst and good practices 10. Standards and GuidelinesThe Second day includes:1. E-waste recycling value chain2. Waste management systems and strategies3. Existing policy concepts and EPR 4. Existing national and international policies5. Materials identifications at XRD LabThe Third day includes:1. Dismantling & ...